首页> 外文期刊>IEEE Spectrum >The DIP may take its final bows: The dual-in-line package, the reigning IC package for several generations, is losing position to newcomers for packaging advanced chips
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The DIP may take its final bows: The dual-in-line package, the reigning IC package for several generations, is losing position to newcomers for packaging advanced chips

机译:DIP可能会屈服:双列直插式封装,几代统治性的IC封装,正在失去包装先进芯片的新手的地位。

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摘要

As the number of leads, or pins, on the dual-in-line package (DIP) increases, its size increases rapidly. DIPs are becoming up to 50 times bigger than the chips themselves, thus defeating the gains of miniaturization resulting from IC advances. A pin-grid array package with leads protruding from the bottom, can handle 256 leads in an area of about 3 square inches. New packages that are becoming available for integrated circuits are described, and the way in which these packages are attached to printed circuit boards is considered. Small-outline integrated circuits, plastic leaded chip carriers, ceramic leaded chip carriers, leadless ceramic chip carriers, and pin-grid arrays are covered. It is pointed out that if metal leads could be eliminated entirely, electrical signal delay and nonuniformity could be greatly reduced. A technique for doing this is tape-automated bonding in which chips may be applied directly to printed-circuit boards.
机译:随着双列直插式封装(DIP)上引线或引脚的数量增加,其尺寸会迅速增加。 DIP正变得比芯片本身大50倍,因此击败了因IC进步而带来的小型化收益。引脚从底部突出的针栅阵列封装可以在大约3平方英寸的区域中处理256条引线。描述了可用于集成电路的新封装,并考虑了将这些封装连接到印刷电路板上的方式。涵盖了小轮廓集成电路,塑料引线芯片载体,陶瓷引线芯片载体,无引线陶瓷芯片载体和针栅阵列。要指出的是,如果可以完全消除金属引线,则可以大大减少电信号延迟和不均匀性。一种实现此目的的技术是胶带自动粘合,其中可以将芯片直接应用于印刷电路板上。

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  • 来源
    《IEEE Spectrum》 |1985年第6期|37-42|共6页
  • 作者

    Bowlby R.;

  • 作者单位

    Motorola Inc., Phoenix, AZ, USA|c|;

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  • 原文格式 PDF
  • 正文语种 eng
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