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High-Density Microvia Technology on Advanced Organic Substrate For Next Generation Flip-Chip Packaging

机译:下一代倒装芯片封装高密度微孔技术

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Meeting the requirements of increasing IC integration and transistor density continues to challenge those involved in package substrate and interconnect technologies. For 45nm-node IC interconnections to area array packages, an I/O pitch of 90μm is required, according to the latest ITRS and iNEMI roadmaps [1,2]. With the projected introduction of 32nm and 22nm IC nodes by 2010, a 20-50μm I/O pad pitch on the IC will necessarily require matching dimensions on the flipchip substrate. Any additional package level integration, such as embedded components, will likely escalate the interconnection demand in the substrate. Sequential build-up organic substrates have been able to meet the wiring demand since their introduction in the early 1990s. However, with the dramatic miniaturization and performance improvement sustained by semiconductor segment, there is a major need to significantly reduce the interconnection dimensions on the package substrate in a relatively short time. In addition to conductor line and space widths, the wiring pitch on the substrate is largely determined by microvia diameter, as well as its capture pad and landing pad diameter. Current state-of-the-art microvia substrates are typically achieving line and space dimensions of 15-20μm with microvia diameters in the range of 60-75μm. The forecasted substrate wiring pitch of 20- 50μm requires multiple layers of materials and high-precision processes for the necessary line/space and microvia dimensions. At this dimensional level, creating the copper interconnects necessary to maintain signal integrity requires materials and process technologies beyond those conventionally used. The build-up dielectric materials are one area where such improvements are currently directed. Equally important are the improved copper plating, photo-imaging, etching and adhesion enhancement technologies that will be required to fabricate such ultrahigh-density organic build-up substrates. This paper presents results from a collaborative research effort focused on fabrication of the next generation of multilayer build-up organic substrates for flip chip applications. Using a new epoxybased dielectric film in combination with state-of-the-art copper electroplating technology, the ability to laser ablate, metalize and fill sub-50μm diameter microvias is demonstrated. Unlike conventional solvent-based materials, this advanced dielectric is the result of the latest developments in epoxy resin-coated copper foil (RCF), using a novel and patented Advanced Dry Epoxy Powder Technology (ADEPT) process for a halogen-free system. In addition, methodologies for forming and filling such microvias, including advanced dielectric metallization and plating techniques are described.
机译:满足升高IC集成和晶体管密度的要求继续挑战涉及封装基板和互连技术的人。对于区域阵列封装的45nm节点IC互连,根据最新的ITRS和Inemi RoadMaps [1,2],需要90μm的I / O间距。随着32nm和22nm IC节点的预计引入2010,IC上的20-50μmI / O焊盘间距将需要在触发器基板上需要匹配的尺寸。任何其他包级集成(例如嵌入式组件)可能会升级基板中的互连需求。自20世纪90年代初以来,顺序积聚有机基板已经能够满足布线需求。然而,随着半导体段持续的剧烈小型化和性能改善,存在主要需要在相对较短的时间内显着减少封装基板上的互连尺寸。除了导体线和空间宽度之外,基板上的布线间距主要由微径径决定,以及其捕获垫和着陆垫直径。目前的最先进的微径底物通常达到15-20μm的线条和空间尺寸,微孔直径在60-75μm的范围内。预测的基板布线间距为20-50μm需要多层材料和高精度工艺,用于必要的线/空间和微径尺寸。在该尺寸级别,创建维持信号完整性所需的铜互连需要超出传统使用的材料和过程技术。积聚介电材料是当前引导的这种改进的一个区域。同样重要的是改进的铜电镀,光学成像,蚀刻和粘合增强技术,以制造这种超高密度有机积聚基板。本文介绍了一项协同研究努力的结果,专注于制造下一代多层积聚有机基板进行倒装芯片应用。使用新的环氧基介电膜与最先进的铜电镀技术组合,对激光烧蚀,金属化和填充亚50μm直径微宽度的能力进行说明。与传统的溶剂基材料不同,这种先进的电介质是环氧树脂涂覆的铜箔(RCF)的最新发育的结果,采用新型和专利的先进的干环氧粉技术(Adept)方法,用于无卤系统。另外,描述了用于形成和填充这种微孔的方法,包括高级电介质金属化和电镀技术。

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