Sub-5.5 FO4 Delay CMOS 64-bit Domino/Threshold Logic Adder Design

摘要

This paper presents the design of a CMOS 64-bit adder using threshold logic gates based on Logical Effort (LE) transistor level delay estimation. The adder is a hybrid design, consisting of domino logic and the recently proposed Charge Recycling Threshold Logic (CRTL). The delay evaluation is based LE modeling of the delay of the domino and CRTL gates. From the initial estimations, the 8-bit sparse carry look-ahead/carry-select scheme has a delay of less than 5.5 FO4 (fan-out-of-four inverter delay), which is more than 1 F04 delay faster than any previously published domino design.