首页>
外国专利>
EFFICIENT THREE-DIMENSIONAL DESIGN FOR LOGIC APPLICATIONS USING VARIABLE VOLTAGE THRESHOLD THREE-DIMENSIONAL CMOS DEVICES
EFFICIENT THREE-DIMENSIONAL DESIGN FOR LOGIC APPLICATIONS USING VARIABLE VOLTAGE THRESHOLD THREE-DIMENSIONAL CMOS DEVICES
展开▼
机译:使用可变电压阈值三维CMOS器件的逻辑应用的高效三维设计
展开▼
页面导航
摘要
著录项
相似文献
摘要
A charge trap field-effect transistor (FET) includes multiple layers of dielectric material defining a charge trapping layer. A p-doped (or n-doped) source region and a p-doped (or n-doped) drain region are connected via a nano-channel, the nano-channel being formed between the multiple layers of dielectric, thus forming a charge trap FET. A charge trap complimentary current field-effect transistor (CFET) includes multiple layers of dielectric material defining a charge trapping layer and includes a 3D charge trap PFET formed with p+ symmetrical source/drain region formed over a 3D charge trap NFET formed with n+ symmetrical source/drain region.
展开▼