Variability Induced by Line Edge Roughness in Silicon on Thin Box (SOTB) MOSFETs

摘要

Intrinsic parameter fluctuations have been regarded as one of the most critical challenges for the future nano-scale CMOS technology. Line-edge-roughness (LER) is caused by the imperfect performance of lithography and etching as well as the discrete nature of material. LER deteriorates device uniformity, especially at the sub-30nm node where critical dimension (CD) is comparable to the scale of correlation length of LER [1]. A thin buried box and an optional back-gate are introduced in SOTB (silicon on thin box) compared to conventional FD-SOI to control device's threshold voltage, power consumption and SCEs (short channel effects) [2] [3]. Gated-LER influences the effective channel length and the extension doping profile beneath the gate, causing a variation in threshold voltage. In this work, we investigate the impacts of LER on 20nm-gate n and p channel SOTB-MOSFETs through a 3D statistical simulation done by ISE TCAD [4]. The influences of gate work-function (WF), box thickness (T_(Box), and back-gate bias (V_(back-gate)) on device's LER-induced variability are also systematically studied. The results are important on optimizing the performance of SOTB MOSFETs for low power application.