With increasing process variations, 1ow-Vt swapping is an effective technique that can be used to improve timing yield without having to modify a design following placement and routing. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for existing low-Vr swapping techniques. This paper presents a simulation-based study that challenges the effectiveness of 1ow-Vt swapping based on the conventional definition of gate criticality, especially as random process variations increase with technology scaling. We introduce dominant gate criticality to address the drawbacks of the conventional definition of gate criticality, and formulate dominant critical gate ranking in the presence of process variations as an optimization problem. Simulation results for 12 benchmark circuits from the ISC AS and OpenSPARC suites to achieve timing yields of 95% and 98% indicate that low-Vr swapping based on dominant gate criticality reduces leakage power overhead by 61% and 42% for independent and correlated process variations, respectively, over low-V_T swapping based on conventional gate criticality.
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