Overwhelming the 0.5 nm EOT Level for CMOS Gate Dielectric

摘要

MOSFET with EOT below 0.37 nm has been achieved with La_2O_3 gate dielectric by realizing direct contact on Si. A sufficient increase in drain current has been observed while scaling the EOT from 0.48 to 0.37 nm. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance. Moreover, the EOT increment by La- silicate formation after high temperature annealing can be well suppressed under control of oxygen by selecting a metal gate.