Exploration on Power Delay Product of Basic Logic Gates for Various CMOS Logic Styles

摘要

Since Power dissipation is one of the important criteria in Low power VLSI design, Chip designers are making lot of efforts to reduce the power dissipation. The power efficiency of any architecture can be explained in terms of power delay product. The circuit which has less PDP is the optimized design. Therefore it is necessary to find the low power CMOS logic design styles for the basic logic gates. The methodology adopted for designing the basic logic gates are CMOS complementary logic, Pseudo nMOS logic, Dynamic CMOS logic styles. The basic logic gates taken for analysis are inverter, NAND and NOR gates. These various logic styles are designed in Cadence Virtuoso ADE L Schematic Editor environment and the technology was chosen as 180nm technology. The power delay product for dynamic CMOS logic inverter, NAND, NOR is found to be 51.35%, 62.81%, 32.4% respectively lesser when compared to the conventional CMOS logic. So out of three proposed three logic styles dynamic CMOS logic styles shows better power delay product.