A novel high speed low power three input static cmos exclusive -or logic gate circuite

摘要

This invention relates to logic gate circuits of digital integrated circuits. It is embodied with multiple inputs particularly showing 3 input circuit which is of static type, consisting of pull up and pull down paths to make the output of the design to "0" or "1* depending on the inputs given to it. The pull up path consists of plurality of p-FET"s; depending on the combination of the inputs given at least three p-FET"s are electrically connected between high supply voltage and the output terminal. Similarly, pull down path consists of plurality of n-FET"s among which three n-FET"s are electrically connected between low supply voltage and the output terminal depending on the inputs applied. Minimum number of pre-charge devices is used by connecting them incisively to all the intermediate nodes of pull up and pull down paths to gain high speed. n-FET"s are used as pre-charge devices in the pull up path whereas, p-FET"s are used as pre-charge devices in the pull down path to charge the intermediate nodes to far supply voltage when they are disconnected from the near supply voltage and the output. Some of the inverted signals are extracted from the circuit itself.