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A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic

机译：一种优化CmOs和BiCmOs组合逻辑中延迟和功率的联合栅尺寸和缓冲器插入方法

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Kerry S. Lowe; P. Glenn Gulak; Senior Member;
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年度 2015
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专利

1. A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic [J] . Lowe K.S., Gulak P.G. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1998,第5期

机译：一种用于优化CMOS和BiCMOS组合逻辑中的延迟和功耗的联合栅极大小调整和缓冲器插入方法
2. A delay model and optimization method of a low-power BiCMOS logic circuit [J] . Shayan Zhang, Kalkur T.S. IEEE Journal of Solid-State Circuits . 1994,第10期

机译：低功耗BiCMOS逻辑电路的延迟模型和优化方法
3. Unified Gate Freezing, Gate Sizing and Buffer Insertion for Low Power CMOS Digital Circuit Design [J] . Hyungwoo Lee, Hakgun Shin, Juho Kim 電子情報通信学会技術研究報告. シリコン材料·デバイス. Silicon Devices and Materials . 2004,第155期

机译：统一的栅极冻结，栅极尺寸调整和缓冲器插入，可实现低功耗CMOS数字电路设计
4. Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits [C] . Lowe, K.S., Gulak, . 1993

机译：门大小调整和缓冲器插入，可优化功率受限的BiCMOS电路的性能
5. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [D] . Xie, Jiani. 2014

机译：用于延迟，面积和功率优化的离散门尺寸调整方法。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CmOs组合逻辑电路的精确动态功耗估计
8. Behavior of faulty double BJT BiCMOS logic gates [R] . Menon, Sankaran M., Malaiya, Yashwant K., Jayasumana, Anura P. 1992

机译：有缺陷的双BJT BiCmOs逻辑门的行为

A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic

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