首页> 外文期刊>Journal of Electronic Materials >Low-Temperature, Strong SiO_(2)-SiO_(2) Covalent Wafer Bonding for III-V Compound Semiconductors-to-Silicon Photonic Integrated Circuits
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Low-Temperature, Strong SiO_(2)-SiO_(2) Covalent Wafer Bonding for III-V Compound Semiconductors-to-Silicon Photonic Integrated Circuits

机译:用于III-V化合物半导体至硅光子集成电路的低温强SiO_(2)-SiO_(2)共价晶圆键合

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摘要

We report a low-temperature process for covalent bonding of thermal SiO_(2) to plasma-enhanced chemical vapor deposited (PECVD) SiO_(2) for Si-compound semiconductor integration. A record-thin interfacial oxide layer of 60 nm demonstrates sufficient capability for gas byproduct diffusion and absorption, leading to a high surface energy of 2.65 J/m~(2) after a 2-h 300 deg C anneal. O_(2) plasma treatment and surface chemistry optimization in dilute hydrofluoric (HF) solution and NH_(4)OH vapor efficiently suppress the small-size interfacial void density down to 2 voids/cm~(2), dramatically increasing the wafer-bonded device yield. Bonding-induced strain, as determined by x-ray diffraction measurements, is negligible. The demonstration of a 50 mm InP epitaxial layer transferred to a silicon-on-insulator (SOI) substrate shows the promise of the method for wafer-scale applications.
机译:我们报告了一种低温过程,用于将热SiO_(2)与用于硅化合物半导体集成的等离子体增强化学气相沉积(PECVD)SiO_(2)共价键合。 60 nm的创纪录的薄界面氧化物层具有足够的气体副产物扩散和吸收能力,经过2 h 300℃退火后,产生了2.65 J / m〜(2)的高表面能。在稀氢氟酸(HF)溶液和NH_(4)OH蒸气中进行O_(2)等离子体处理和表面化学优化可有效地将小尺寸界面空隙密度抑制至2个空隙/ cm〜(2),从而显着增加了与晶片的键合设备成品率。通过X射线衍射测量确定的键合引起的应变可以忽略不计。将50 mm InP外延层转移到绝缘体上硅(SOI)衬底上的演示证明了该方法在晶圆级应用中的前景。

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