A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

摘要

This paper describes the challenges of testing low-power designs that use the commonly used Multi-Supply Multi-Voltage (MSMV) and Power Shut-Off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.