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Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler
Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler
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机译:使用设计编译器在异步时钟域边界进行多电压优化的层次结构分离方法
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摘要
This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.
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