A detailed 3D-NEGF simulation study of tunnelling in n-Si nanowire MOSFETs

摘要

Nanowire field-effect transistors (NWT) attract significant interest as strong contenders for future CMOS applications [1]. Their superior electrostatic integrity offers ultimate-scaling solutions [1]. They will be needed near the end of the current edition of the ITRS when the channel length of the transistor crosses the 10nm mark. In fact, 5nm channel length Si NWTs have been recently demonstrated experimentally [2-4]. Strong quantum confinement and tunnelling in such devices calls for full-scale quantum transport (QT) simulations. Previous simulations have shown that source-to-drain tunnelling starts to play an important role at channel lengths below 10 nm. The source-drain tunnelling increases leakage current but also enhances significantly the on-current, due to the narrowing of the source drain potential barrier at high drain voltage. The on-current enhancement persists at relatively large channel lengths. At the same time, strong degradation in the sub-threshold slope is expected as the channel length of the device shrinks. Therefore the optimal design of nanowire MOSFETs in the near-ballistic regime of operation requires a careful trade off between the detrimental tunnelling-related increase of the leakage current in the sub-threshold regime and the enhancement of the on-current at large drain bias conditions. Bearing in mind the above observations it is somewhat surprising that a systematic study of tunnelling as a function of channel length and cross-sectional size and bias conditions is somewhat lacking in the literature. We try to fill this gap by presenting a systematic study of the tunnelling in a Gate-Ail-Around (GAA) nanowire transistor. In this study we concentrate purely on the analysis of the source-to-drain tunnelling neglecting scattering from surface roughness or discrete dopants.