In this paper, the analysis and lab correlation are performed for supply noise and its impact on jitter and system margin with regular versus reduced on-die decap for two multi-Gb/s high speed serial links. Power delivery noise is simulated with highly distributed models for on-chip network, package and motherboard for different scenarios, and elaborate analyses are provided. For various operational cases, on-die supply noise, full-link system margin, Rx jitter tolerance, and Tx jitter are measured in lab. Both simulations and lab measurement demonstrate the effects of simultaneous switching noise, power management sequencing control, and on-die decap reduction, and show the similar trends. Higher noise corresponds to jitter increase and full-link margin degradation. The validated methodology can optimize PDN design and supply noise induced jitter/margin.
展开▼
