Noise and Jitter Characterization of High-Speed Interfaces in Heterogeneous Integrated Systems

摘要

Heterogeneous integration allows multiple silicon dies of various technologies and complexity to communicate efficiently using second-level interconnects, interposers, in a single package. The interposer also provides a low-impedance power delivery path between multiple independent power domains. Although the channels are very short and the signal integrity is not a challenge, the huge increase in the transient current of multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multidie systems. In this article, accurate analysis and characterization techniques of noise and jitter in multidie interfaces are presented. Power supply noise and empirically derived jitter models are correlated with measurements and detailed transistor-level circuit simulations, respectively.