Ultra-deep sub-micron technologies are more vulnerable to different types of uncertainties. In this paper, we introduce a novel methodology to estimate the vulnerability of sequential circuits to soft errors at gate level. A new probabilistic modeling of SET propagation is proposed, which reduces the complexity of unrolling sequential circuits. This approach enables a multi-cycle error propagation analysis of sequential circuits using only two copies of the circuit combinational part. The proposed probabilistic modeling is based on the proposed backward unrolling approach in conjunction with the proposed formulation of SET propagation into a Satisfability problem by utilizing satisf ability modulo theories. Useful information about the SET latency in sequential circuits and the minimum unrolling required to observe the actual behavior of the circuit is generated. These results are then used to estimate the circuit soft error rate. Experimental results demonstrate the effectiveness and applicability of the proposed approach.
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