Circuit arrangement with clock-signal detection device e.g. for memory devices such as CMOS type, includes clock signal ascertainment device for detecting whether clock signal is present at terminal

摘要

A circuit arrangement (1) having at least one terminal (3b) to which a clock/data signal (/CLK,/CLKt) can be applied. The circuit arrangement in addition has a clock-signal-ascertaining-device (2) for ascertaining whether a clock signal (/CLK,/CLKt) is present at the terminal (3b). An Independent claim is included for a semiconductor component i.e. a DDR (double data rate) component, especially a memory component, such as a DRAM..