Clock signal input/output device for clock signal correction e.g. for semiconductor memory device, has frequency divider, signal integrator and two signal receiver circuits coupled to signal restoration circuit

摘要

The clock signal input/output device (1) has the received clock signal fed via a frequency divider (4) to a signal integrator (6), which is followed by a pair of identical signal receiver circuits (8,9), connected to a signal restoration circuit (11) delivering the clock output signal, the opposing signal flanks of which are triggered in response to signal flanks of the respective signals provided by the signal receiver circuits. An independent claim for a clock signal correction method is also included.