Signal integrity and simultaneous switching noise of CMOS devices and systems.

摘要

A method of calculating Simultaneous Switching Noise (SSN) for Complementary Metal Oxide Semiconductor (CMOS) based systems has been developed and investigated in detail. This model includes output driver negative feedback effects, where as previous models do not include these effects. Several closed-form equations were derived to incorporate negative feedback effects in SSN calculations. Results were compared with the well referenced circuit simulator SPICE, and with measured values. A method of modeling effective inductance of the {dollar}Vsb{lcub}DD{rcub}/Vsb{lcub}SS{rcub}{dollar} chip-package interface has been developed. This model includes the effects of package pin placement, and perforations (if any) in {dollar}Vsb{lcub}DD{rcub}/Vsb{lcub}SS{rcub}{dollar} planes. These models have been implemented in a SSNS (Simultaneous Switching Noise Simulator) architecture. This architecture can be used for calculating SSN for CMOS single packaged chip, or multi-chip assemblies (i.e. MCM, COB, and etc). Device and package interconnect scaling rules were employed to verify performance degradation and limits due to chip-package parasitics. Results were compared using approximate and detailed University of Arizona (UA) simulation tools, and future trends are predicted.; Also, detailed investigations were performed to characterize signal propagation over perforated reference {dollar}(Vsb{lcub}DD{rcub}/Vsb{lcub}SS{rcub}){dollar} planes. A scaled-up model, and a periodically perforated FR-4 card structure were fabricated, and modeled using 2-D, 3-D and S-parameter extraction tools. Simulation results were compared with TDR measured values.; Mechanisms which cause false switching due to the chip-package and package-system interface-generated noise were analyzed. Impact of coupled and SSN on digital systems was investigated using noise immunity characteristics of CMOS input receivers. Output driver design techniques, such as damping and/or skewing output switching waveform to reduce SSN, were analyzed and design guidelines/rules-of-thumb have been developed. Application specific circuit design techniques to reduce SSN are explained.