FUNCTIONAL VERIFICATION METHOD OF AN INTEGRATED CIRCUIT MODEL FOR CONSTITUTING A VERIFICATION PLATFORM, EMULATOR EQUIPMENT AND VERIFICATION PLATFORM.

摘要

The present invention relates to a method for functional verification of a software model (40) of an integrated circuit on demand (ASIC), in low level language (such as for example of HDL type) treating the establishment separately. of the model and the development of functional verification tests to be applied to the circuit model to constitute a verification platform comprising the following two stages: - constitution of an autonomous circuit emulator (1) obtained by replacing the model by low-level language (of HDL type) of physical description of the circuit in project to be validated, by a high-level abstract description (for example C ++) generating response data structures conforming to the functional specification (20) of the project in function of the stimuli received, this mode being called “emission mode”, - integration of the software model (40) in low level language (of HDL type) of the circuit resulting from the project in a pla te-form of verification, and constitution of the connection of the autonomous circuit emulator (1), previously validated, in parallel on the interfaces of the software model (40) of the circuit, and of the connection of an environment emulator (11 , 21,22), and- use of this platform as a reference for the validation of the response data transmitted by the software model (40) of the circuit, this mode being called "verification mode".