Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices

摘要

A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.