Parallel Bit Test mode circuit providing for data writing to the memory cells by Mode Register Set for test of semiconductor memory device and test method thereof by the Parallel Bit Test mode

摘要

PURPOSE: A parallel bit test mode circuit capable of performing the data write operation by a mode register set for test, a semiconductor memory device provided with the same and a method for testing the same are provided to freely write various data pattern. CONSTITUTION: A parallel bit test mode circuit capable of performing the data write operation by a mode register set for test includes a mode register set(MRS) pattern selection block, a data pattern generation block and a parallel bit test(PBT) data multiplexing block. The MRS pattern selection block receives the test MRS code carrying a predetermined flag information for informing the use of MRS pattern and a predetermined data pattern to be written on the selected memory cell array during the write operation of the PBT mode test and generates the input data multiplexing control signal corresponding to the predetermined flag information. The data pattern generation block receives the test MRS code and sets the plurality bits of the registers corresponding to the predetermined data pattern. The data patter generation block outputs each data of the registers. And, the parallel data multiplexing block receives the output data and outputs the received data when the input data multiplexing control signal is active.