首页> 外国专利> Method of forming a low-k dielectric CVD film having an in-situ embedded nanolayer to improve mechanical properties (dielectric stack and method of forming and interconnect structure including the dielectric stack)

Method of forming a low-k dielectric CVD film having an in-situ embedded nanolayer to improve mechanical properties (dielectric stack and method of forming and interconnect structure including the dielectric stack)

机译:形成具有原位嵌入式纳米层以改善机械性能的低k介电CVD膜的方法(介电堆叠以及包括该介电堆叠的形成和互连结构的方法)

摘要

A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.
机译:具有约3.0或更小的有效介电常数k的低k介电堆叠,其中通过将至少一个纳米层引入介电堆叠来改善堆叠的机械性能。在不显着增加叠层内薄膜的介电常数且无需对本发明的介电叠层进行任何后处理步骤的情况下,就可以实现机械性能的改善。具体地,本发明提供了一种低k电介质堆叠,其包括至少一种低k电介质材料和存在于至少一种低k电介质材料中的至少一个纳米层。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号