Using the number of times a processor has to wait for a response to determine an efficiency metric and an operational characteristic for the processor

摘要

Disclosed is an apparatus that may dynamically adjust processor CPU performance. The apparatus has a counter, an efficiency determination module, and a management module. The counter determines the number of time an event occurs, each occurrences is a processor component (e.g., a processor core) awaiting or waiting for a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences, in preset a time interval. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. The component is a core of a multi-core processor and each core may have its own power control apparatus. The operational characteristics include the power state, the clock frequency and/or the supply voltage. The events may be memory and/or input/output communications. The apparatus may include a temperature sensor to provide the management module with temperature data, so that the module can determine the available headroom of the processor ie if the power of the processor can be increased without the processor overheating.