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Multi-Port Register File with an Input Pipelined Architecture and Asynchronous Read Data Forwarding
Multi-Port Register File with an Input Pipelined Architecture and Asynchronous Read Data Forwarding
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机译:具有输入流水线架构和异步读取数据转发的多端口寄存器文件
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摘要
In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.
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