MIPI D-PHY circuit for Low-power mode

摘要

The present invention relates to a D-PHY circuit for a MIPI operating in a low-power (LP) mode, and one embodiment of the present invention includes a low power transmitter for adjusting a rate of change of a full swing output voltage in a maximum current amount range, A D-PHY circuit for a MIPI operating in a low power mode comprising a low power receiver receiving a swing output voltage and generating a predetermined full swing logic output based on a first reference voltage and a second reference voltage, have. The D-PHY circuit for MIPI operating in the low power mode according to an embodiment of the present invention can handle asynchronous instructions with a maximum 10 Mbps speed and 1.2 V voltage swing among the MIPI D-PHY analog block for high performance low power interface .