首页> 外国专利> LAMINATED SINTERED CERAMIC WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE CONTAINING WIRING SUBSTRATE

LAMINATED SINTERED CERAMIC WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE CONTAINING WIRING SUBSTRATE

机译:叠层烧结陶瓷布线基板,以及包含布线基板的半导体封装

摘要

In this laminated sintered ceramic wiring substrate, at least some of an in-plane conductor is fine-lined. Nevertheless, the cross-sectional shape of the fine-lined in-plane conductor is made into a trapezoid; and the height of the cross-section of the trapezoidal shape (a), the length of the lower base (c) and the length of the upper base (d), and the spacing (b) between the lower bases of cross-sections of trapezoidal shapes of in-plane conductors that are adjacent within a plane parallel to the main surface of the substrate are configured so as to satisfy a specific relation. It is thereby possible to minimize problems such as a wiring often becoming open (broken) or becoming less reliable in a high-temperature/high-humidity environment. The present invention provides a laminated sintered ceramic wiring substrate that has a low incidence of defects relating to open or shorted circuits, while also having excellent high-humidity/high-moisture reliability, despite having a fine wiring layer. A faster, more compact, lower-profile (thinner), high-reliability semiconductor package is provided by using this wiring substrate.
机译:在该层叠烧结陶瓷配线基板中,至少一部分面内导体被细线化。但是,将细线状的面内导体的截面形状设为梯形。梯形形状的横截面高度(a),下底边的长度(c)和上底边的长度(d),以及下边底边之间的间距(b)在与基板的主表面平行的平面内相邻的面内导体的梯形形状中的任意一个构成为满足特定的关系。从而可以使诸如在高温/高湿环境下配线经常断路(断线)或可靠性降低之类的问题最小化。本发明提供了一种层压烧结陶瓷布线基板,其具有与开路或短路有关的缺陷的发生率低,并且尽管具有精细的布线层,但也具有优异的高湿/高湿可靠性。通过使用该布线基板,可以提供更快,更紧凑,外形更薄(更薄)的高可靠性半导体封装。

著录项

  • 公开/公告号EP2753159B1

    专利类型

  • 公开/公告日2018-12-19

    原文格式PDF

  • 申请/专利权人 NGK INSULATORS LTD.;

    申请/专利号EP20110871755

  • 申请日2011-08-29

  • 分类号H05K3/46;H01L23/528;H05K1/02;H01L23/498;H01L23/522;

  • 国家 EP

  • 入库时间 2022-08-21 12:30:48

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