COMPUTATIONAL MODELING OF HOT-SPOT IDENTIFICATION AND CONTROL IN 3-D STACKED CHIPS WITH INTEGRATED COOLING

摘要

In 3-D chip stacks, the electronic design may lead to a variety of different hot-spot scenarios and through-silicon-via (TSV) arrangements and distributions. In the present work, the influence and implications of the integrated water-cooling, TSV distribution, and size on the control of inhomogeneous hot-spots in such stacks is investigated. The numerical model consists of a row of 50 inline cylindrical micropin fins (of different size) inside a microcavity. Material properties are modeled as temperature-dependent, and the Reynolds number ranges from 60 to 180. An optimal design of hot-spots arrangements and TSV sizes is found to reduce the maximal temperature in the chip by up to 20%, and increase the average heat transfer by up to 30%.