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首页> 外文期刊>ECS Journal of Solid State Science and Technology >Anomalous Gate Current Hump after Dynamic Negative Bias Stress and Negative-Bias Temperature-Instability in p-MOSFETs with Hf_xZr_(1-x)O_2 and HfO_2/Metal Gate Stacks
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Anomalous Gate Current Hump after Dynamic Negative Bias Stress and Negative-Bias Temperature-Instability in p-MOSFETs with Hf_xZr_(1-x)O_2 and HfO_2/Metal Gate Stacks

机译:具有Hf_xZr_(1-x)O_2和HfO_2 /金属栅叠层的p-MOSFET在动态负偏置应力和负偏置温度不稳定性之后的异常栅极电流驼峰

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In this study, the authors investigated an anomalous gate current hump after dynamic negative bias stress (NBS) and negative-bias temperature-instability (NBTI) in Hf_xZ_(1-x)O_2 and HfO_2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. This result is attributed to hole trapping in high-k bulk. Measuring gate current under initial through body floating and source/drain floating conditions indicates that holes flow from source/drain to gate. The fitting of the gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction under initial. Next, fitting the gate current after dynamic NBS and NBTI indicates Frenkel-Poole then tunneling mechanisms, finally returning to the Frenkel-Poole mechanism. These phenomena can be attributed to hole trapping in high-k bulk and the formula E_(high-k) ε(high-k) = Q + E_(sio2εSiO_2). To further understand the gate current hump, both Zr-undoped and 8 ~ 10% Zr-doped in high-k bulk devices were used for comparisons. These results indicate that initial gate current is also a significant factor in generating the anomalous gate current hump, and all results obey the hump generation condition of J_(Tunneling) J_(Freenkei -Poole) --
机译:在这项研究中,作者研究了Hf_xZ_(1-x)O_2和HfO_2 /金属栅p沟道金属氧化物-中的动态负偏置应力(NBS)和负偏置温度不稳定性(NBTI)后的异常栅极电流驼峰。半导体场效应晶体管。此结果归因于高k体中的空穴陷阱。在初始通过体浮置和源极/漏极浮置条件下测量栅极电流表明,空穴从源极/漏极流向栅极。栅极电流-栅极电压特性曲线的拟合表明,在初始状态下,Frenkel-Poole机制主导了传导。接下来,在动态NBS和NBTI之后拟合栅极电流表示Frenkel-Poole,然后是隧穿机制,最后返回Frenkel-Poole机制。这些现象可归因于高k体中的空穴陷阱,公式E_(high-k)ε(high-k)= Q + E_(sio2εSiO_2)。为了进一步了解栅极电流驼峰,在高k体器件中使用了无Zr掺杂和8%至10%的Zr掺杂进行比较。这些结果表明,初始栅极电流也是产生异常栅极电流驼峰的重要因素,所有结果均符合J_(Tunneling) J_(Freenkei -Poole)的驼峰生成条件-

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