Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

摘要

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm(2). At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are mea-sured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 mu W corresponding to 67 fJ/conversion step figure of merit.