Performance of Carrier Synchronization for 2(4)-PSK-Modulation Using First-Order Digital Phase-Locked Loop

摘要

The performance degradation caused by the nonideal carrier phase recovery in a coherent 2(4)-PSK-receiver is investigated. A decision-directed digital phase-locked loop (DD-DPLL) estimates the carrier phase from the incoming signal, which is corrupted by additive white gaussian noise. The phase error process is modelled by a markoff chain. Performance measures are the phase error variance, the bit error rate (BER) and the mean time to slip from one stable lock point to another.