Formal value-range and variable testability techniques for high-level design-for-testability

摘要

This research applies formal dataflow analysis and techniques to high-level DFT. Our proposed approach improves testability of the behavioral-level circuit description (such as in VHDL) based on propagation of the value ranges of variables through the circuit's Control-Data Flow Graph (CDFG). The resulting testable circuit is accomplished via controllability and observability computations from these value ranges and insertion of appropriate testability enhancements, while keeping the design area-performance overhead to a minimum.