Design and Optimization of 6T FinFET SRAM in 45 nm Technology

摘要

Scaling of the Standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current. To minimize short channel effects, double gate FinFET are used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, 6T FinFET SRAM is designed using shorted gate. Sub-threshold leakage current and gate leakage current of Double gate FinFET SRAM are observed and are compared with the conventional structure of 6T SRAM cell. We have applied self controllable voltage level technique on DG FinFET SRAM cell and leakage current is observed. It was observed that the total leakage current of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique. Simulation is performed with cadence virtuoso tool in 45 nm technology.