Hardware Architecture Design for High-performance H.264/AVC Deblocking Filter

摘要

In multimedia imaging/video compression systems, the block-based discrete cosine transform (BDCT) is widely applied to conversion and compression. During the quantization of compression, after processing with an inverse discrete cosine transform (IDCT), a certain defect emerges in BDCT, i.e., two adjacent blocks fail to be perfectly joined together. This block effect of the picture undermines the video quality and tends to become more pronounced as the sampling factor increases. In image decoding, a deblocking filter requires an enormous amount of computation. If the computation is carried out entirely by software, a large system bandwidth will inevitably be occupied. To overcome this problem, the design of a suitable hardware architecture is urgently required. In this study, we proposed the use of the system bus and a low-memory, low-cost, and effective deblocking filter architecture to reduce the operation time of the deblocking filter. In contrast to existing hardware architectures, the design proposed in this paper adopts dual-port static random access memory (SRAM) and two-port SRAM architectures, thereby storing data via a new data reading approach, to save transposed memory and reduce the hardware size. By coupling the proposed architecture with parallel processing units, the processing speed will be increased.