Wafer-Testing of Optoelectonic–Gigascale CMOS Integrated Circuits

摘要

Gigascale integration (GSI) chips with high bandwidth, integrated optoelectronics (OE), and photonic components are an emerging technology. In this paper, we present the prospects and opportunities for wafer-testing of chips with electrical and optical I/O interconnects. The issues and requirements of testing OE–GSI ICs during high-volume manufacturing are identified and discussed. Two probe substrate technologies based on microelectromechanical systems (MEMS) for simultaneously interfacing with a multitude of surface-normal optical I/Os and high-density electrical I/Os are detailed. The first probe substrate comprises vertically compliant probes for contacting electrical I/Os and grating-in-waveguide I/Os for optical probing. The second MEMS probe module uses microsockets and through-substrate interconnects to contact pillar-shaped electrical and optical I/Os and to redistribute signals, respectively.