METHOD FOR TESTING CMOS INTEGRATED CIRCUIT AND CMOS INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To facilitate testing on a CMOS integrated circuit in a shorter time by further simplifying test patterns in a method, in which the leak current IDDQ flowing to a power supply terminal is measured for detecting the fault of the CMOS integrated circuit. ;SOLUTION: Decoders 21, 22, and 23 for test mode are added to decoders 9, 10, and 11 for selecting register address and the outputs of the decoders 9, 10, and 11 and 21, 22, and 23 are connected to registers 6a-6d, 7a-7d, and 8a-8d via off-gates G1-G12. Therefore, the quality deciding tests conducted on a CMOS integrated circuit by using a power supply current can be performed effectively with high quality in a sufficiently short time, by easily setting the internal state of the circuit in a plurality of patterns for IDD quiescent tests in a very short time, because the outputs of the decoders 9-11 and 21-23 can be written collectively in the registers 61-63, 71-7d, and 81-8d made into a group.;COPYRIGHT: (C)1999,JPO