A LOW NOISE, HIGH-SPEED COMPENSATED CMOS OP-AMP DESIGN TECHNIQUE

摘要

In this paper, we have proposed a new methodology for the design of low frequency, low noise and high speed compensated CMOS op-amp which specifies open loop circuit parameters to obtain enhanced gain, settling time and closed loop stability. The op-amp which we have designed consists of an Operational Transconductance Amplifier (OTA) followed by an output buffer. The OTA design involves the use of a continuous-time Common mode feedback circuit which maintains the output common voltage at the required level while maximizing the output swing and the desired compensation is done with a capacitor connected between the input and output of the buffer. The low noise high speed Op-Amp is designed using 180nm CMOS technology and exhibits 88 dB DC gain. For a parallel combination of 2 pF and 1 k? load, the unity gain frequency and phase margin are found to be 251 MHz and 37o respectively. Under the same load condition, the proposed compensation method results in a roughly 1.8 times increase in unity gain frequency i.e 392 MHz and a 33o improvement in the phase margin as compared to the conventional approach.