机译:由于Pt偏析,Ni(Pt)Si触点以PtSi为主的肖特基势垒高度
Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson,Texas 75080, USA;
Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson,Texas 75080, USA;
Division of Materials Science and Engineering, University of California at Davis, Davis, California 95616,USA;
Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson,Texas 75080, USA;
Advanced CMOS, Texas Instruments Incorporated, Dallas, Texas 75243, USA;
Advanced CMOS, Texas Instruments Incorporated, Dallas, Texas 75243, USA;
Advanced CMOS, Texas Instruments Incorporated, Dallas, Texas 75243, USA;
Advanced CMOS, Texas Instruments Incorporated, Dallas, Texas 75243, USA;
Advanced CMOS, Texas Instruments Incorporated, Dallas, Texas 75243, USA;
Division of Materials Science and Engineering, University of California at Davis, Davis, California 95616,USA;
School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA;
Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson,Texas 75080, USA;
机译:具有耗尽型PtSi肖特基势垒触点和掺杂剂隔离功能的全耗尽UTB和Trigate N沟道MOSFET
机译:降低肖特基势垒高度的两种不同方案在NiSi / Si和PtSi / Si界面处的杂质偏析的比较研究
机译:通过硫偏析获得的Ni_xPt_(1-x)Si / n-Si接触具有小于0.1 eV的有效肖特基势垒高度
机译:Ni和Pt锗化物/ n-Ge接触的肖特基势垒高度调整
机译:介电偶极子减轻了肖特基势垒高度调整,从而降低了接触电阻。
机译:硼铝双重注入与微波退火相结合对NiSi / Si接触处肖特基势垒高度的调节
机译:通过增加PtSi肖特基势垒源极/漏极FET中的衬底掺杂来降低肖特基势垒高度
机译:ptsi-si肖特基势垒接触的氢退火