在应用FPGA进行DDS系统设计过程中,选择芯片的运行速度优化和资源利用优化常常是相互矛盾的,从发展趋势和运算要求看,系统速度指标的意义比面积指标更趋重要.基于此,介绍了一种流水线结构来优化传统的相位累加器,在QuartusⅡ开发环境下搭建系统模型、仿真及下载,并采用嵌入式逻辑分析仪分析和验证了实验结果.该系统可以完成多位频率控制字的累加,能够产生正弦波、方波和三角波,具有良好的实时性.%In the process of DDS system design by using FPGA, the chip selection for its speed optimization and resource utilization optimization is often contradictory. As for trends and operational requirements, the significance of system speed index is more important than the area index. In the light of this, a pipeline architecture is adopted to optimize the conventional phase accumulator. The system model was built, simulated and downloaded in quartus Ⅱ development environment. The experimental results were verified with an embedded logic analyzer. The results indicate that the system can complete the summation of frequency control word, produce sine, square and triangular waves, and has a good real-time performance.
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