用于超低频信号测量的高精度低功耗增量式模数转换器

摘要

An incremental analog-to-digital converter (I-ADC) with chopper stabilization (CHS) and self-calibration techniques is presented to meet the requirements of high resolution,low power consumption and small area for measuring devices of ultra-low-frequency signals.The I-ADC has the function of reset operation to avoid pattern noise caused by ultra-low-frequency signals.A first-order architecture is adopted for the I-ADC to reduce power consumption and chip area,and to achieve 14-bit resolution by increasing certain conversion time.The chopper stabilization technique is employed to eliminate the influence of amplifier's low-frequency noise and offset on the I-ADC's precision,and power-on self-calibration is employed to eliminate the systematic offset of the I-ADC.The circuit of the I-ADC and the layout of the modulator are designed with the DongBu 0.5 μm BCD technology.Simulation results in an input range of -156.25～156.25 mV show that the maximum absolute conversion error of the I-ADC is 21 μV,the maximum errors of differential nonlinearity and integral nonlinearity are 0.12 and 0.21 bit,respectively,and the average current consumption of the modulator is only 20 μA.The modulator occupies a chip area of only 150 μm × 310 μm.The proposed I-ADC achieves 14 bit resolution,which is required by ultra-low-frequency signal measuring systems,such as lithiumion battery coulometer,and has significant advantages of low power consumption and small area.%针对超低频信号测量装置对模数转换器(ADC)的高精度、低功耗和小面积要求,提出了一种带有斩波稳零(CHS)和自校准技术的增量式模数转换器(I-ADC).I-ADC带有复位操作,可避免超低频信号带来的模式噪声.为了尽量降低功耗和芯片面积,I-ADC采用一阶结构,并通过增加一定的转换时间来实现14 bit的转换精度.该I-ADC采用斩波稳零技术来消除运放低频噪声和失调对其精度的影响,I-ADC的系统失调则采用上电自校准技术来消除.采用DongBu 0.5 μm BCD工艺完成了I-ADC电路及其调制器版图的设计.仿真结果表明:在-156.25～156.25 mV输入范围内,I-ADC转换误差的绝对值最大为21 μV,微分非线性误差的绝对值最大为0.12 bit,积分非线性误差的绝对值最大为0.21 bit,调制器的平均电流消耗仅为20 μA;调制器的版图面积仅为150 μm×310 μm;所设计的I-ADC可满足锂电池电量计等超低频测量系统所需的14 bit转换精度,并具有显著的低功耗和小面积优势.