一种高速并行位同步结构

摘要

For bit synchronization in high-rate data transmission demodulator , a high-speed parallel architecture is presented. Filter coefficient is updated real -time to realize filter, interpolation, Decimation, and the output speed of filter banks is reduced to symbol rate. The calculation and realization for filter coefficient is given. Analysis shows the parallel architecture has low real-time computational complexity.%针对高速数据解调器中的位同步,给出一种高速并行结构.通过实时更新滤波器系数,同时实现滤波、内插、抽取功能,滤波器组输出速率降低为符号速率.给出了滤波器系数的计算过程及具体方法,分析结果表明该并行结构有效的降低了实时运算的复杂度.