Conventional memories technologies such as SRAM, DRAM, and NAND flash are facing formidable device scaling challenges. Various new non-volatile memory (NVM) technologies have emerged recently, including spin-torque-transfer random access memory (STT-RAM), phase-change memory (PCM), and resistive random access memory memory (ReRAM). Among them, ReRAM stands out due to its simple structure, low programming voltage, fast switching speed , high on/off ratio, excellent scalability, good endurance and great compatibility with the silicon CMOS technology. Although the initial target of ReRAM is NAND flash replacement, ReRAM holds the potential to revolutionize the memory hierarchy from the last-level cache to mass storage system. Through years' efforts from both academia and industry, Gb-scale prototype ReRAM prototypes have been demonstrated. However, most of ReRAM research has still been focused on device-level development. As the ultimate goal of ReRAM research is to advance ReRAM in current memory hierarchy, the key question is how to architect ReRAM in different levels of the memory hierarchy. The work in this dissertation aims to address these issues.;First, several array/macro ReRAM models with different simulation accuracy and speed requirement are built and validated. Second, circuit-/architecture-level techniques that mitigate the large overhead in straightforward implementation of ReRAM prototypes are proposed and evaluated. Third, architectural-level case studies of adopting ReRAM in main memory and storage system are conducted. Fourth, the impact of cell failures in ReRAM design is analyzed and efficient hard error diction unit is proposed.
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