Low power and process variation aware SRAM and Cache design fault tolerance in SRAM circuit, architecture and organization.

摘要

Dealing with SRAMs and Caches reliability and power consumption issues in the nano scaled technology nodes has proven to be a major challenge. On one side the increased gate and sub-threshold leakage of the memory cells combined with the memory hungry nature of SOCs (memory structures account for major portion of silicon real state) has made the power consumption of the caches (specially that of leakage power) to be comparable or even dominating in comparison with the SOC dynamic power consumption. On the other hand the dense structure of the memories and the usage of minimum sized transistors have raised serious reliability issues in nano-scaled geometries where the parametric process variation poses strong spread in the physical and in turn logical characteristic of the transistors devices.;Problem becomes more complicate since the reliability and the power consumption of the memories could not be addressed independently. Voltage Scaling is the most effective knob to control both dynamic and leakage power consumption as both leakage and dynamic power consumption are reduced super linearly with linear reduction in the supplied voltage. Voltage scaling, when applied to the memories, exponentially increases the memory cell failure probability, severely limiting the application of these techniques. Chapter 1 of this dissertation provide a trough background review of the effect of voltage scaling on the reliability of the memories and characterizes the memory behavior when operated at different voltages and frequencies. Chapters 2 to 5 explain different solutions for realizing voltage scalable SRAM/Cache architectures with great tolerance against reliability issues posed by process variation. Each organization/architecture address the reliability issue from a different perspective, covering a range of circuit technique (in CP-Cache) to organizational and architectural techniques (such as in VTD-Cache and IDC-Cache).