Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan;
CMOS digital integrated circuits; analogue-digital conversion; capacitor switching; digital-analogue conversion; low-power electronics; DAC capacitor array; SFDR measurement; SNDR; analog-to-digital converter; low-power low-cost digital CMOS process; power 6.8 mW; set-and-down capacitor switching method; size 0.18 mum; successive approximation register; time-interleaving SAR ADC;
机译:在90nm数字CMOS中配置SAR ADC的6位50-MS / s阈值
机译:在65nm CMOS中具有133fF输入电容和37fJ / conv FOM的220-MS / s 9位2X时间交错SAR ADC
机译:带有智能投机双击嵌入式DFE的6位1.5 GS / S SAR ADC,用于有线接收器应用的130nm CMOS中
机译:在0.18-μm数字CMOS过程中的6位220 ms / s时间交错SAR ADC
机译:采用SIGE BiCMOS技术的高速SAR ADC设计
机译:使用标准的0.18-μmCMOS工艺制造的微磁场传感器
机译:10位10-MS / S 0.18-㎛CMOS异步SAR ADC,具有基于分型基于电容的差分DAC