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1.
Implementation of 6-Port 3D transformer in injection-locked frequency divider
机译:
注入锁定分频器中6端口3D变压器的实现
作者:
Sheng-Lyang Jang
;
Chia-Wei Tai
;
Cheng-Chen Liu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
field effect MMIC;
frequency dividers;
microwave oscillators;
transformers;
voltage-controlled oscillators;
6-Port 3D transformer;
CMOS LC-tank ILFD tuning;
frequency 3 GHz;
frequency 4.81 GHz to 5.3 GHz;
frequency 8.9 GHz to 11.9 GHz;
injection-locked frequency divider;
nMOS-core cross-coupled VCO;
power 1.02 mW;
voltage 0.6 V;
CMOS;
VCO;
locking range;
stacked 3-dimensional transformer;
2.
Enabling technologies for multi-chip integration using Proximity Communication
机译:
使用邻近通信实现多芯片集成的技术
作者:
Chow A.
;
Hopkins D.
;
Drost R.
;
Ho R.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
integrated circuit interconnections;
multichip modules;
radio links;
chip-to-chip input-output;
multichip integration;
multichip package;
proximity communication;
3.
A compact rail-to-rail buffer with current positive-feedback for LCD source driver
机译:
具有电流正反馈功能的紧凑型轨到轨缓冲器,用于LCD源驱动器
作者:
Jia-Hui Wang
;
Hao-Yuan Zheng
;
Chien-Hung Tsai
;
Chin-Tien Chang
;
Ching-Chung Lee
;
Chen-Yu Wang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
buffer circuits;
driver circuits;
feedback amplifiers;
LCD source driver;
active matrix liquid crystal display source driver;
compact rail-to-rail buffer;
current positive-feedback;
quiescent current;
4.
Words from symposium chair and co-chair
机译:
座谈会主席和共同主席的话
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
5.
Static and dynamic test power reduction in scan-based testing
机译:
基于扫描的测试中的静态和动态测试功耗降低
作者:
Sying-Jyan Wang
;
Shun-Jie Huang
;
Li K.S.-M.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
SPICE;
boundary scan testing;
leakage currents;
BPTM;
dynamic power reduction;
leakage current;
nanometer technology;
power consumption;
scan-based testing;
size 22 nm;
static power reduction;
6.
Digital PWM controller for SIDO switching converter with time-multiplexing scheme
机译:
具有时分复用方案的SIDO开关转换器的数字PWM控制器
作者:
Chi-Wai Leng
;
Chun-Hung Yang
;
Chien-Hung Tsai
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
DC-DC power convertors;
PWM power convertors;
digital control;
multiplexing;
switching convertors;
DC-DC converters;
SIDO switching converter;
digital PWM controller;
discontinuous-conduction mode;
look-up table;
single-inductor dual-output converter;
system-on-chip integration;
time-multiplexing scheme;
7.
Past, present and future of RF design in wireless communication
机译:
无线通信中射频设计的过去,现在和未来
作者:
Chien G.
;
Loh K.L.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
antennas;
radiocommunication;
transceivers;
RF design;
RF transceiver design;
antenna;
baseband signal processing unit;
wireless communication;
8.
iScan: Indirect-access scan test over HOY test platform
机译:
iScan:通过HOY测试平台进行的间接访问扫描测试
作者:
Chao-Wen Tzeng
;
Chun-Yen Lin
;
Shi-Yu Huang
;
Chih-Tsun Huang
;
Jing-Jia Liou
;
Hsi-Pin Ma
;
Po-Chiun Huang
;
Cheng-Wen Wu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
automatic testing;
integrated circuit testing;
HOY test platform;
dynamic packet formatting;
iScan;
indirect access scan test;
primary input data encoding;
Indirect-Access Testing;
Scan Test;
Test Compression;
9.
Copyright
机译:
版权
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
analogue-digital conversion;
phase locked loops;
system-on-chip;
video signal processing;
ADC;
PLL;
chip-to-chip interconnection;
clocking;
data converters;
divider;
image processing;
low power analog technique;
millimeter wave design;
next generation high performance CPU;
regulators;
system on chip;
video processing;
voltage control oscillator;
10.
Toward the integration of incremental physical synthesis optimizations
机译:
整合增量物理综合优化
作者:
Nam G.-J.
;
Papa D.
;
Moffitt M.
;
Alpert C.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
circuit optimisation;
integrated circuit design;
linear programming;
logic design;
microprocessor chips;
timing;
high frequency microprocessor design;
incremental optimization;
incremental physical synthesis optimization;
physical optimization;
standard cell library;
timing improvement;
11.
Single-instruction based programmable memory BIST for testing embedded DRAM
机译:
基于单指令的可编程存储器BIST,用于测试嵌入式DRAM
作者:
Chung-Fu Lin
;
Jen-Chieh Ou
;
Meng-Hsueh Wang
;
Yu-Sen Ou
;
Ming-Hsin Ku
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
DRAM chips;
built-in self test;
embedded systems;
integrated circuit design;
integrated circuit testing;
system-on-chip;
BIST design;
SoC design;
complex integration environment;
dense embedded memory;
eDRAM macro;
embedded DRAM testing;
single-instruction based programmable memory;
supported memory testing algorithm;
two-level address generator;
12.
A 1.55ns 0.015 mm
2
64-bit quad number comparator
机译:
1.55ns 0.015 mm
2 sup> 64位四进制比较器
作者:
Minsu Kim
;
Joo-Young Kim
;
Hoi-Jun Yoo
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
comparators (circuits);
logic circuits;
64-bit quad number comparator;
bit-wise comparing logic chain;
sequential strobes;
time 1.55 ns;
13.
A comprehensive linear-regression-based Procedure for inductor parameter extraction
机译:
基于电感器参数提取的基于线性回归的综合程序
作者:
Ruinan Chang
;
Wenjun Zhang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
equivalent circuits;
inductors;
parameter estimation;
inductor parameter extraction;
linear-regression-based procedure;
on-chip inductors;
self-resonant frequencies;
symmetric inductors;
14.
An area efficient shared synapse cellular neural network for low power image processing
机译:
用于低功率图像处理的区域有效共享突触细胞神经网络
作者:
Jinwook Oh
;
Seungjin Lee
;
Joo-Young Kim
;
Hoi-Jun Yoo
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
cellular neural nets;
image processing;
real-time systems;
sample and hold circuits;
cellular neural network;
current holder circuit;
low power image processing;
sample-and hold circuit;
synapse multiplier;
15.
Built-in self-repair techniques for content addressable memories
机译:
内置的自我修复技术,可寻址内容的存储器
作者:
Guan-Quan Lin
;
Zhen-Yu Wang
;
Shyue-Kung Lu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
content-addressable storage;
block-level replacement technique;
built-in self-repair technique;
content addressable memory;
16.
Design of high-speed errors-and-erasures Reed-Solomon decoders for multi-mode applications
机译:
用于多模式应用的高速误差和擦除的Reed-Solomon解码器设计
作者:
Yung-Kuei Lu
;
Ming-Der Shieh
;
Wen-Hsuen Kuo
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
Reed-Solomon codes;
error correction codes;
high-speed techniques;
high-speed errors-and-erasures Reed-Solomon decoders;
multi-mode applications;
reformulated inversionless Berlekamp-Massey algorithm;
17.
Allocation of scratch-pad memory in priority-based multi-task systems
机译:
在基于优先级的多任务系统中分配暂存器内存
作者:
Hideki Takase
;
Tomiyama H.
;
Takada H.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
integer programming;
memory architecture;
multiprogramming;
instruction memory;
multi-task systems;
scratch-pad memory;
18.
Software-enabled design visibility enhancement for failure analysis process improvement
机译:
支持软件的设计可视性增强,可改进故障分析流程
作者:
Chia-Chih Yen
;
Shen-Tien Lin
;
Kai Yang
;
Peillat J.
;
Gibson P.
;
Auvray E.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CAD;
failure analysis;
fault tolerant computing;
CAD tools;
design functionality;
failure analysis process improvement;
feature design comprehension;
logic tracing capability;
pre-silicon design behavior;
seamless visibility enhancement environment;
silicon signals;
software-enabled design visibility enhancement;
19.
A low-jitter all-digital phase-locked loop using a suppressive digital loop filter
机译:
使用抑制型数字环路滤波器的低抖动全数字锁相环
作者:
Hsuan-Jung Hsu
;
Shi-Yu Huang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
digital phase locked loops;
oscillators;
all-digital phase-locked loop;
digital loop filter;
digitally controlled oscillator;
frequency 200 MHz;
frequency 53 MHz to 560 MHz;
low-jitter phase-locked loop;
20.
Timing control degradation and NBTI/PBTI tolerant design for Write-replica circuit in nanoscale CMOS SRAM
机译:
纳米级CMOS SRAM写复制电路的时序控制性能下降和NBTI / PBTI容错设计
作者:
Shyh-Chyi Yang
;
Hao-I Yang
;
Ching-Te Chuang
;
Wei Hwang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
SRAM chips;
timing circuits;
CMOS technology node poly-gate;
GND;
NBTI/PBTI tolerant design;
SRAM write operations;
high-k metal-gate models;
inactive timing-critical circuits;
multibank architecture;
nanoscale CMOS SRAM;
negative-bias temperature instability;
performance degradation;
positive-bias temperature instability;
threshold voltage drifts;
timing control degradation;
virtual supply line;
write margin;
write-replica circuit;
write-replica timing control scheme;
21.
An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-µm CMOS
机译:
采用0.13μmCMOS的18.7mW 10GHz锁相环电路
作者:
I-Wei Tseng
;
Jen-Ming Wu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
current-mode logic;
frequency dividers;
phase locked loops;
voltage-controlled oscillators;
CMOS;
VCO;
current mode logic;
frequency 10 GHz;
frequency divider;
gain-boosting design;
high speed networking;
phase-locked loop circuit;
power 18.7 mW;
power consumption reduction;
size 0.13 mum;
true single phase clock logic;
voltage 1.2 V;
Phase-Locked Loop (PLL);
True Single Phase Clock (TSPC);
current mode logic (CML);
gain boosting;
22.
A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture
机译:
具有低复杂度LLR架构的高吞吐量radix-4 log-MAP解码器
作者:
Hsiang-Tsung Chuang
;
Kai-Hsin Tseng
;
Wai-Chi Fang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
maximum likelihood decoding;
turbo codes;
MAP decoder;
UMC standard cell technology;
critical path delay;
hardware complexity;
high-throughput radix-4 log-MAP decoder;
hybrid 4-input addition-subtraction structure;
log-likelihood ratio;
low complexity LLR architecture;
radix-4 recursion architecture;
size 0.13 mum;
trace-back architecture;
turbo decoder;
23.
Content-aware energy prediction for video streaming in mobile devices
机译:
移动设备中视频流的内容感知能量预测
作者:
Yi-Chan Li
;
Hisu-Hsien Li
;
Han-Lin Li
;
Chia-Lin Yang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
mobile communication;
multimedia communication;
video streaming;
content aware energy prediction;
energy-aware;
mobile devices;
multimedia devices;
video playback;
24.
Logic synthesis for better than worst-case designs
机译:
逻辑综合性能优于最坏情况的设计
作者:
Cong J.
;
Minkovich K.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
circuit optimisation;
logic design;
BTWLibMap;
clock period;
library mapping algorithm;
logic optimization operation;
logic synthesis;
timing error;
worst-case delay;
25.
Leakage reduction, variation compensation using partition-based tunable body-biasing techniques
机译:
使用基于分区的可调整人体偏置技术减少泄漏,补偿变化
作者:
Po-Yuan Chen
;
Chiao-Chen Fang
;
TingTing Hwang
;
Hsi-Pin Ma
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
Monte Carlo methods;
leakage currents;
network synthesis;
leakage current;
leakage reduction;
partition-based tunable body-biasing techniques;
slow circuits;
variation compensation;
26.
A third-order continuous-time sigma-delta modulator for Bluetooth
机译:
用于蓝牙的三阶连续时间sigma-delta调制器
作者:
Wen-Lin Yang
;
Wen-Hung Hsieh
;
Chung-Chih Hung
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
Bluetooth;
CMOS integrated circuits;
digital-analogue conversion;
integrated circuit design;
modulators;
sigma-delta modulation;
CMOS;
clock jitter;
digital-to-analog converter;
distributed feedback;
power 22.2 mW;
size 0.18 mum;
third-order continuous-time sigma-delta modulator;
voltage 1.8 V;
27.
An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance
机译:
一种有效的多相测试技术,可以完美地防止过度检测出可接受的故障,从而通过容错来优化产量
作者:
Tong-Yu Hsieh
;
Kuen-Jong Lee
;
Breuer M.A.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
automatic test pattern generation;
fault simulation;
integrated circuit testing;
integrated circuit yield;
ATPG;
acceptable fault detection;
error tolerance;
multiphase test technique;
optimal yield improvement;
over detection prevention;
28.
Rewired retiming for free flip-flop reductions without delay penalty
机译:
有线重新定时,可免费减少触发器,而不会增加延迟
作者:
Mingqi Jiang
;
Wai-Chung Tang
;
Young E.F.Y.
;
Wu Y.L.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
circuit optimisation;
integrated circuit design;
integrated circuit interconnections;
logic design;
free flip-flop reduction;
interconnect delays;
retimed clock;
retiming flow;
rewired retiming method;
29.
On chip Communication-Architecture Based Thermal Management for SoCs
机译:
基于片上通信架构的SoC热管理
作者:
Gupta A.
;
Pasricha S.
;
Dutt N.
;
Kurdahi F.
;
Khouri K.
;
Abadir M.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
computer architecture;
system-on-chip;
thermal analysis;
on chip communication-architecture;
sensor;
systems-on-chip design;
temperature aware traffic flow;
thermal management;
30.
A case study on MPEG4 decoder design with SystemBuilder
机译:
用SystemBuilder设计MPEG4解码器的案例研究
作者:
Shibata S.
;
Honda S.
;
Tomiyama H.
;
Takada H.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
codecs;
field programmable gate arrays;
logic design;
video coding;
FPGA;
MPEG4 decoder design;
pipelined hardware implementation;
system builder;
system-level design toolkit;
31.
Prefetching for array data in embedded Java hardware accelerator
机译:
在嵌入式Java硬件加速器中预取数组数据
作者:
Yi-Ruei Wu
;
Yu-Sheng Chen
;
Shann J.J.-J.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
Java;
hardware-software codesign;
storage management;
array data;
embedded Java;
hardware accelerator;
suitable array prefetching;
32.
Panel discussion
机译:
小组讨论会
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
33.
2009 international symposium on VLSI design, automation and test organization
机译:
2009 VLSI设计,自动化和测试组织国际研讨会
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
34.
Incremental physical design method for flat SOC design
机译:
平面SOC设计的增量物理设计方法
作者:
Li-Yi Lin
;
Hsin-Chang Lin
;
Shih-Arn Hwang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
consumer electronics;
logic design;
system-on-chip;
consumer electronic;
decoding;
flat SoC design;
incremental physical design method;
next generation multimedia chip;
signal processing hardware engine;
video-audio encoding;
35.
On the complexity of the Port Assignment Problem for Binary Commutative Operators in high-level synthesis
机译:
高级综合中二元交换算子端口分配问题的复杂性
作者:
Brisk P.
;
Ienne P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
multiplexing equipment;
binary commutative operators;
high-level synthesis;
multiplexers;
port assignment problem complexity;
36.
Segment based X-Filling for low power and high defect coverage
机译:
基于分段的X填充,可实现低功耗和高缺陷覆盖率
作者:
Zhen Chen
;
Dong Xiang
;
BoXue Yin
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
program testing;
defect coverage;
multiple scan chains;
scan based testing;
segment based X-filling;
test patterns;
test power;
test process;
37.
Power and noise aware test using preliminary estimation
机译:
使用初步估算的功率和噪声感知测试
作者:
Noda K.
;
Ito H.
;
Hatayama K.
;
Aikyo T.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
automatic test pattern generation;
boundary scan testing;
design for testability;
ATPG;
DFT;
IR-drop;
clock cycle;
noise aware scan test method;
power aware scan test method;
power consumption;
preliminary estimation;
38.
An area-efficient parallel Turbo decoder based on contention free algorithm
机译:
基于无竞争算法的高效区域并行Turbo解码器
作者:
Kai-Hsin Tseng
;
Hsiang-Tsung Chuang
;
Shao-Yen Tseng
;
Wai-Chi Fang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
decoding;
simulated annealing;
turbo codes;
area-efficient extrinsic memory schemes;
area-efficient parallel turbo decoder;
contention free algorithm;
memory collision problem;
simulated annealing algorithm;
39.
Design and analysis of 1–60GHz, RF CMOS peak detectors for LNA calibration
机译:
用于LNA校准的1–60GHz RF CMOS峰值检波器的设计和分析
作者:
Jayaraman K.
;
Khan Q.A.
;
Chiang P.
;
Baoyong Chi
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
integrated circuit design;
low noise amplifiers;
peak detectors;
voltage-controlled oscillators;
LNA calibration;
RF CMOS peak detectors;
VCO;
frequency 1 GHz to 60 GHz;
frequency 2.4 GHz;
frequency 55 GHz to 60 GHz;
peak detector circuit topologies;
size 180 nm;
Calibration;
Low Noise Amplifiers (LNA);
Peak detector;
40.
Semiconductor industry prosperity trough deeper horizontal collaborations
机译:
半导体行业繁荣通过更深层次的横向合作
作者:
Iizuka T.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
management;
semiconductor industry;
cost sharing structure;
horizontal collaborations;
horizontal cooperation;
value generation;
vertically integrated model;
41.
A g
m
/ID-based synthesis tool for pipelined analog to digital converters
机译:
基于g
m inf> / ID的综合工具,用于流水线模数转换器
作者:
Ya-Ting Shyu
;
Cheng-Wu Lin
;
Jin-Fu Lin
;
Soon-Jyh Chang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
analogue-digital conversion;
electronic design automation;
integrated circuit design;
pipeline arithmetic;
analog circuit sizing;
circuit-design experience;
circuit-level synthesis tool;
design automation methodology;
gm/ID-based synthesis tool;
pipelined ADC;
pipelined analog to digital converters;
satisfactory circuit performance;
top-down systematic design procedure;
42.
A current compensated reference oscillator
机译:
电流补偿参考振荡器
作者:
Wan-Jing Li
;
Soon-Jyh Chang
;
Ying-Zu Lin
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
Monte Carlo methods;
integrated circuit reliability;
oscillators;
reference circuits;
Monte Carlo simulation;
current-compensated reference oscillator reliability;
digital CMOS process;
power 0.5 mW;
process-and-supply voltage variations;
size 0.18 mum;
stable oscillation frequency;
temperature variations;
voltage 1.8 V;
43.
Table of content
机译:
表中的内容
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
44.
A bias-driven approach for automated design of operational amplifiers
机译:
偏置驱动的运算放大器自动设计方法
作者:
Cheng-Wu Lin
;
Pin-Dai Sue
;
Ya-Ting Shyu
;
Soon-Jyh Chang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
differential amplifiers;
operational amplifiers;
fully-differential operational amplifier design;
layout generation;
lookup-table-based scheme;
transistor-level automation;
45.
Adaptive Simulated Annealer for high level synthesis design space exploration
机译:
自适应模拟退火炉,用于高级综合设计空间探索
作者:
Schafer B.C.
;
Takenaka T.
;
Wakabayashi K.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
high level synthesis;
simulated annealing;
adaptive simulated annealer;
high level synthesis design space exploration;
46.
Virtual prototyping increases productivity - A case study
机译:
虚拟样机可提高生产率-案例研究
作者:
Avss P.
;
Prasant S.
;
Jain R.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
time to market;
virtual prototyping;
SoC;
consumer products;
embedded code;
embedded memories;
embedded software;
instruction set simulators;
microcontrollers;
product development flow;
productivity;
reference models;
sequential development flow;
simulating processors;
software development;
software model;
system engineering;
time-to-market requirements;
time-to-market schedules;
virtual system prototyping;
47.
Glass carrier SOP technology demonstrated by design of a 19 GHz 3.8 dB CMOS LNA
机译:
玻璃载波SOP技术通过19 GHz 3.8 dB CMOS LNA设计证明
作者:
Aspemyr L.
;
Sjoland H.
;
Berthiot D.
;
Proot J.-P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS analogue integrated circuits;
field effect MIMIC;
flip-chip devices;
integrated circuit design;
low noise amplifiers;
low-power electronics;
system-on-package;
CMOS chip;
SOP;
current 5 mA;
flip-chip mounting;
frequency 19 GHz;
frequency 19.2 GHz;
gain 7 dB;
glass carrier;
integrated passive components;
low-noise amplifier;
low-power amplifier;
noise figure 3.8 dB;
power gain;
size 0.13 mum;
voltage 1.2 V;
BCB;
LNA;
48.
Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems
机译:
带有内置自检/自诊断和故障隔离电路的容错路由器,用于基于2D网格的芯片多处理器系统
作者:
Shu-Yen Lin
;
Wen-Chung Shen
;
Chan-Cheng Hsu
;
Chih-Hao Chao
;
An-Yeu Wu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
built-in self test;
fault tolerance;
multiprocessing systems;
network-on-chip;
2D-mesh;
built-in self-diagnosis;
built-in self-test;
chip multiprocessor systems;
fault-isolation circuits;
fault-tolerant router;
on-chip networks;
49.
VLSI design of spread spectrum encoding low power RFID tag baseband processor
机译:
扩频编码低功耗RFID标签基带处理器的VLSI设计
作者:
Zhu Qiuling
;
Zhang Chun
;
Wang Xiaohui
;
Wang Ziqiang
;
Li Fule
;
Wang Zhihua
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
VLSI;
encoding;
error statistics;
low-power electronics;
microprocessor chips;
radiofrequency identification;
reliability;
signal processing;
spread spectrum communication;
1P6M CMOS technology;
VLSI design;
bit error rate;
low-power RFID tag baseband processor;
power 8.8 muW;
power-saving strategy;
security;
size 0.18 mum;
spread spectrum encoding;
voltage 1.04 V;
50.
Efficient two-layered cycle-accurate modeling technique for processor family with same instruction set architecture
机译:
具有相同指令集架构的处理器系列的高效两层周期精确建模技术
作者:
Chien-De Chiang
;
Juinn-Dar Huang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
instruction sets;
logic design;
microprocessor chips;
cycle accurate modeling;
inner functional kernel;
instruction set architecture;
outer timing shell;
processor family;
51.
A continuous-time delta-sigma modulator using feedback resistors
机译:
使用反馈电阻的连续时间delta-sigma调制器
作者:
Yung-Chou Lin
;
Wen-Hung Hsieh
;
Chung-Chih Hung
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
circuit feedback;
circuit optimisation;
continuous time systems;
delta-sigma modulation;
jitter;
low-power electronics;
operational amplifiers;
resistors;
ENOB;
Gm-C integrator;
NTF zero optimization;
active-RC OpAmp;
active-RC integrator;
bandwidth 1 MHz;
clock jitter sensitivity;
feedback resistor;
nonreturn-to-zero pulse shaping;
power 13.7 mW;
size 0.18 mum;
standard digital CMOS process;
storage capacity 10 bit;
third-order continuous-time delta-sigma modulator;
voltage 1.8 V;
Gm-;
52.
An all-digital clock generator for dynamic frequency scaling
机译:
用于动态频率缩放的全数字时钟发生器
作者:
Wei-Ming Lin
;
Chao-Chyun Chen
;
Shen-Iuan Liu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
clocks;
delay lines;
power aware computing;
all-digital clock generator;
cyclic clock multiplier;
dynamic frequency scaling;
53.
The future of semiconductor industry - A foundry's perspective
机译:
半导体行业的未来-铸造厂的观点
作者:
Fang-Churng Tseng
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
economics;
foundries;
semiconductor industry;
TSMC;
co-optimization;
design productivity;
design technology;
design waste;
economical ups and downturns;
foundry;
open innovation platform;
54.
Exploiting advanced fault localization methods for yield u00026; reliability learning on SoCs
机译:
开发高级故障定位方法以提高产量SoC上的可靠性学习
作者:
Appello D.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
VLSI;
fault diagnosis;
integrated circuit reliability;
integrated circuit yield;
system-on-chip;
SoC reliability;
SoC yield;
VLSI CMOS technology;
fault localization method;
industrial methodology;
Fault localization;
diagnosis;
yield and reliability;
55.
A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs
机译:
片上网络监控基础架构,用于以通信为中心的嵌入式多处理器SoC调试
作者:
Vermeulen B.
;
Goossens K.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
embedded systems;
microprocessor chips;
network-on-chip;
system-on-chip;
SoC;
communication-centric debug;
debug engineers;
design for debug;
embedded multi-processor;
network-on-chip monitoring infrastructure;
system on chip;
56.
Foreword
机译:
前言
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
57.
A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process
机译:
一个0.18 µm数字CMOS工艺的6位220-MS / s时间交织SAR ADC
作者:
Chun-Cheng Liu
;
Yi-Ting Huang
;
Guan-Ying Huang
;
Soon-Jyh Chang
;
Chung-Ming Huang
;
Chih-Haur Huang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
analogue-digital conversion;
capacitor switching;
digital-analogue conversion;
low-power electronics;
DAC capacitor array;
SFDR measurement;
SNDR;
analog-to-digital converter;
low-power low-cost digital CMOS process;
power 6.8 mW;
set-and-down capacitor switching method;
size 0.18 mum;
successive approximation register;
time-interleaving SAR ADC;
58.
A 6-bit 1GS/s low-power flash ADC
机译:
一个6位1GS / s低功耗闪存ADC
作者:
Yu-Chang Lien
;
Ying-Zu Lin
;
Soon-Jyh Chang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
low-power electronics;
ultra wideband technology;
CMOS process;
UWB systems;
effective number of bit;
high speed ADC;
input bandwidth;
low power consumption;
low-power design guideline;
low-power flash ADC;
resolution bandwidth;
sampling frequency;
59.
From living faster to living better
机译:
从更快生活到更好生活
作者:
de Vries R.P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
integrated circuit technology;
semiconductor industry;
semiconductor technology;
IC industry;
Moore's law productivity gains;
consumer demand shift;
digital processors;
productive consumer electronics;
semiconductor development;
semiconductor world paradigm shift;
smart products;
60.
System-level development and verification framework for high-performance system accelerator
机译:
高性能系统加速器的系统级开发和验证框架
作者:
Chen-Chieh Wang
;
Ro-Pun Wong
;
Jing-Wun Lin
;
Chung-Ho Chen
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
logic design;
network interfaces;
virtual machines;
MD5 algorithm;
QEMU-SystemC;
electronic system level platform;
high-performance system accelerator;
software/hardware communication;
verification framework;
virtual machine;
61.
Author index
机译:
作者索引
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
62.
A practical power model of AMBA system for high-level power analysis
机译:
用于高级功率分析的AMBA系统的实用功率模型
作者:
Sung-Che Li
;
Wei-Ting Liao
;
Mu-Shun Lee
;
Wen-Tsan Hsieh
;
Liu C.-N.J.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
power consumption;
system-on-chip;
AMBA system;
communication architecture;
high-level power analysis;
practical power model;
63.
Design of a dual-mode baseband receiver for 802.11n and 802.16e MIMO OFDM/OFDMA
机译:
用于802.11n和802.16e MIMO OFDM / OFDMA的双模基带接收机的设计
作者:
Hsiao C.
;
Chi-Yun Chen
;
Chiueh T.-D.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
MIMO communication;
OFDM modulation;
WiMax;
block codes;
channel estimation;
interference suppression;
radio receivers;
space-time codes;
wireless LAN;
wireless channels;
802.11n;
EWC HT PHY V1.27;
IEEE 802.16e-2005;
MIMO OFDM receiver;
MIMO OFDMA receiver;
MIMO STBC;
PHY baseband simulation model;
V-BLAST;
dual-mode baseband receiver;
dynamic channel estimation;
inter-carrier interference cancellation hardware;
mobile channels;
static channel estimation;
64.
A memory-efficient architecture for low latency Viterbi decoders
机译:
低延迟Viterbi解码器的内存高效架构
作者:
Yun-Ching Tang
;
Do-Chen Hu
;
Weiyi Wei
;
Wen-Chung Lin
;
Hongchin Lin
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
Viterbi decoding;
convolutional codes;
memory architecture;
CMOS technology;
convolutional code;
low latency Viterbi decoders;
memory-efficient architecture;
modified state exchange;
pretrace back technique;
survival state number;
65.
Challenges in microprocessor physical and power management design
机译:
微处理器物理和电源管理设计中的挑战
作者:
Konstadinidis G.K.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
integrated circuit layout;
low-power electronics;
microprocessor chips;
CPU design;
circuit design;
layout-dependent effects;
microprocessor physical design;
power density;
power management design;
process scaling;
66.
Hierarchical architecture for network-on-chip platform
机译:
片上网络平台的分层体系结构
作者:
Lianq-Yu Lin
;
Huang-Kai Lin
;
Cheng-Yeh Wang
;
Lan-Da Van
;
Jing-Yang Jou
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
network-on-chip;
bandwidth penalty;
communication amount;
communication data contention;
hierarchical 2D mesh network-on-chip platform;
hierarchical architecture;
system data transmission behavior modeling;
task binding method;
67.
Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition
机译:
具有超小电容以检测ESD过渡的片上电源轨ESD钳位电路的设计
作者:
Shih-Hung Chen
;
Ming-Dou Ker
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
capacitance;
detector circuits;
electrostatic discharge;
ESD transition;
fast power-on condition;
on-chip power-rail ESD clamp circuit;
ultra-small capacitance;
68.
A 200-Mb/s 10-mW super-regenerative receiver at 60 GHz
机译:
200 GHz的200Mb / s 10mW超再生接收器
作者:
Kung-Hao Liang
;
Chen L.
;
Yue C.P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
MIMIC;
receivers;
CMOS technology;
MIMIC receivers;
bit rate 200 Mbit/s;
current 10 mA;
frequency 60 GHz;
power 10 W;
short-range communication;
size 65 nm;
super-regenerative receiver;
voltage 1 V;
69.
Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband(IR-UWB) transceivers
机译:
脉冲无线超宽带(IR-UWB)收发器中用于多径干扰消除的发射机均衡
作者:
Changhui Hu
;
Redfield S.
;
Huaping Liu
;
Khanna R.
;
Nejedlo J.
;
Chiang P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
interference suppression;
radio transmitters;
transceivers;
ultra wideband communication;
CMOS 2-tap equalizer;
CMOS technology;
current mode logic;
impulse radio transceivers;
multipath interference cancellation;
pulse sign inversion;
pulse tap delay control;
pulse width control;
signal-to-noise improvement;
transmitter equalization;
ultra-wideband transceivers;
70.
2.4 GHz low-pass filters with harmonic suppression using integrated passive device process
机译:
具有集成无源器件工艺的谐波抑制功能的2.4 GHz低通滤波器
作者:
Hsin-Chia Lu
;
Jhih-Kuan Wu
;
Chuan Pan
;
Chia-Wen Chiang
;
Huan-Chun Fu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
capacitors;
inductors;
low-pass filters;
frequency 2.4 GHz;
insertion loss;
integrated passive device process;
shunt capacitors;
transmission zeros;
BCB;
integrated passive device;
low-pass filter;
71.
A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13µm CMOS
机译:
采用0.13µm CMOS的6GS / s,6位,全速可测试ADC和DAC对
作者:
Chen-Kang Ho
;
Hao-Chiao Hong
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS logic circuits;
analogue-digital conversion;
current-mode logic;
design for testability;
ADC;
CMOS;
DAC;
current mode logics;
design-for-testability circuits;
digital-analogue conversion;
signal-to-noise ratio;
size 0.13 mum;
spurious-free dynamic range;
GS/s;
at-speed tests;
flash ADC;
72.
A 0.35µm CMOS divide-by-3 LC injection-locked frequency divider
机译:
0.35μmCMOS 3分频LC注入锁定分频器
作者:
Sheng-Lyang Jang
;
Chuang-Jen Huang
;
Cheng-Chen Liu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
UHF frequency convertors;
frequency dividers;
injection locked oscillators;
microwave frequency convertors;
voltage-controlled oscillators;
CMOS process;
divide-by-3 LC-tank injection-locked frequency divider;
double cross-coupled complementary MOSFET LC-tank oscillator;
frequency 3.18 GHz to 3.316 GHz;
frequency 9.14 GHz to 10.03 GHz;
power 8 mW;
resonator inductors;
self-oscillating VCO;
signal injection;
size 0.35 mum;
third-harmonic input;
voltage 2.0 V;
CMOS;
LC-tank oscillator;
divid;
73.
Low-voltage transformer-based CMOS VCOS and frequency dividers
机译:
基于低压变压器的CMOS VCOS和分频器
作者:
Ng A.W.L.
;
Sujiang Rong
;
Hui Zheng
;
Luong H.C.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
coupled circuits;
feedback oscillators;
frequency dividers;
voltage-controlled oscillators;
low-voltage transformer-based CMOS VCO;
phase noise;
transformer-coupled circuit techniques;
transformer-feedback techniques;
74.
A 57-GHz CMOS VCO with 185.3 tuning-range enhancement using tunable LC source-degeneration
机译:
使用可调谐LC信号源退化,具有185.3%的调谐范围增强功能的57 GHz CMOS VCO
作者:
Chuan-Wei Tsou
;
Chi-Chen Chen
;
Yo-Sheng Lin
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
circuit tuning;
integrated circuit design;
millimetre wave integrated circuits;
millimetre wave oscillators;
millimetre wave transistors;
voltage-controlled oscillators;
CMOS VCO;
cross-coupled transistor pair;
frequency 57 GHz;
tunable LC source-degeneration;
tuning-range enhancement;
varactor;
voltage-controlled oscillator;
75.
Novel FFT processor with parallel-in-parallel-out in normal order
机译:
新型FFT处理器,具有按正常顺序并行输入并行输出
作者:
Hsiang-Sheng Hu
;
Hsiao-Yun Chen
;
Shyh-Jye Jou
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
OFDM modulation;
channel estimation;
fast Fourier transforms;
microprocessor chips;
mobile communication;
radiocommunication;
CMOS;
FFT;
IEEE 802.16e;
OFDM communication system;
discrete Fourier transform;
frequency 160 MHz;
frequency 83.3 MHz;
parallel-in-parallel-out in normal order;
power 21.7 mW;
processor;
size 90 nm;
time 7.3 mus;
voltage 1 V;
76.
Improved SPICE macromodel of phase change random access memory
机译:
相变随机存取存储器的改进SPICE宏模型
作者:
Huan-Lin Chang
;
Hung-Chih Chang
;
Shang-Chi Yang
;
Hsi-Chun Tsai
;
Hsuan-Chih Li
;
Liu C.W.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
SPICE;
crystallisation;
integrated circuit modelling;
phase change memories;
SPICE macromodel;
crystallization time;
falling edge problem;
phase change random access memory;
77.
Transforming RF and mm-Wave CMOS circuits
机译:
转换RF和毫米波CMOS电路
作者:
Niknejad A.M.
;
Chowdhury D.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
field effect MIMIC;
low-power electronics;
millimetre wave power amplifiers;
radiofrequency amplifiers;
transformers;
AC coupling;
RF building blocks;
impedance matching;
integrated circuit transformers;
low-voltage digital CMOS technology;
mm-wave CMOS circuits;
power amplifier design;
78.
Visual prostheses: Current progress and challenges
机译:
视觉假体:当前的进展和挑战
作者:
Theogarajan L.
;
Shire D.
;
Kelly S.
;
Wyatt J.L.
;
Rizzo J.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
eye;
prosthetics;
chronic retinal implant;
post- op;
visual prostheses;
79.
Circuit acyclic clustering with input/output constraints and applications
机译:
具有输入/输出约束和应用的电路非循环聚类
作者:
Rung-Bin Lin
;
Tsung-Han Lin
;
Shin-An Wu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
circuit simulation;
combinational circuits;
logic design;
circuit acyclic clustering;
combinational circuit i;
input-output constraint;
logic simulation;
80.
Coupling- and ECP-aware metal fill for improving layout uniformity in copper CMP
机译:
具有耦合和ECP意识的金属填充物,用于改善铜CMP中的布局均匀性
作者:
Yu-Lun Co
;
Hung-Ming Chen
;
Yi-Kan Cheng
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
chemical mechanical polishing;
coupled circuits;
crosstalk;
electroplating;
filler metals;
surface topography;
ECP-aware metal fill;
chip surface topography;
copper CMP;
coupling capacitances;
coupling noise problems;
coupling-aware metal fill;
crosstalk noise problems;
density-driven metal fill;
floating dummy metals;
layout uniformity;
81.
A detailed router for hierarchical FPGAs based on simulated evolution
机译:
基于模拟演进的用于分层FPGA的详细路由器
作者:
Ke Zhu
;
Yici Cai
;
Qiang Zhou
;
Xianlong Hong
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
field programmable gate arrays;
network routing;
optimisation;
critical path delay;
detailed router;
hierarchical FPGA;
hierarchical field programmable gate array;
rip-up priority function;
routing algorithm;
simulated evolution optimization technique;
time consumption;
wire length;
82.
Refinement and reuse of TLM 2.0 models: The key for ESL success
机译:
完善和重用TLM 2.0模型:ESL成功的关键
作者:
Reyes V.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
circuit CAD;
semiconductor device models;
semiconductor industry;
virtual prototyping;
ESL design methods;
SystemC;
TLM 2.0 models;
multidimensional problem;
83.
Low-power 48-GHz CMOS VCO and 60-GHz CMOS LNA for 60-GHz dual-conversion receiver
机译:
适用于60 GHz双转换接收器的低功耗48 GHz CMOS VCO和60 GHz CMOS LNA
作者:
Yo-Sheng Lin
;
Tien-Hung Chang
;
Chang-Zhi Chen
;
Chi-Chen Chen
;
Hung-Yu Yang
;
Wong S.S.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
MMIC power amplifiers;
field effect MIMIC;
low noise amplifiers;
low-power electronics;
millimetre wave oscillators;
phase noise;
radio receivers;
voltage-controlled oscillators;
CMOS LNA;
compression point;
dual-conversion receiver;
figure-of-merit;
frequency 1 MHz;
frequency 48 GHz;
frequency 57 GHz to 64 GHz;
frequency 60 GHz;
gain 10.7 dB to 18.8 dB;
input return loss;
input third-order inter-modulation point;
loss -10.6 dB to -37.4 dB;
low-noise amplifier;
low-power CMOS VCO;
low-power l;
84.
A wireless power telemetry with self-calibrated resonant frequency
机译:
具有自校准谐振频率的无线电力遥测
作者:
Wei-Jen Huang
;
Chein-Lung Chen
;
Shen-Iuan Liu
会议名称:
《》
|
2009年
关键词:
CMOS integrated circuits;
calibration;
coils;
frequency measurement;
radiotelemetry;
CMOS I/O pads;
CMOS process fabrication;
frequency calibration;
inductive primary coil;
secondary coil resonant frequency;
self-calibrated resonant frequency;
size 0.35 mum;
wireless power telemetry;
85.
Miniature 60-GHz-band bandpass filter with 2.55-dB insertion-loss using standard 0.13 µm CMOS technology
机译:
微型60 GHz带通滤波器,采用标准0.13 µm CMOS技术,具有2.55 dB的插入损耗
作者:
Mei-Ching Lu
;
Jin-Fa Chang
;
Li-Chun Lu
;
Yo-Sheng Lin
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
band-pass filters;
integrated circuit design;
microstrip filters;
microstrip lines;
millimetre wave filters;
millimetre wave integrated circuits;
CMOS technology;
bandpass filter;
circuit design;
frequency 60 GHz;
insertion-loss;
loss 2.55 dB;
microstrip-line;
optimized ground-plane pattern;
size 0.13 mum;
60-GHz-band;
CMOS;
integrated filter;
low insertion loss;
miniature;
86.
Cost efficient FEQ implementation for IEEE 802.16a OFDM transceiver
机译:
IEEE 802.16a OFDM收发器的经济高效FEQ实现
作者:
Chih-Hsien Lin
;
Yi-Hsien Lin
;
Chih-Feng Wu
;
Muh-Tian Shiue
;
Chorng-Kuang Wang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
OFDM modulation;
VLSI;
channel estimation;
equalisers;
fading channels;
field programmable gate arrays;
metropolitan area networks;
transceivers;
FEQ implementation;
FPGA board;
IEEE 802.16a OFDM transceiver;
SR transformation;
VLSI design memory arrangement;
WMAN SNR loss;
channel estimation filtering;
metropolitan area network;
multipath fading channel;
single-tap frequency-domain equalizer;
strength reduction transformation;
87.
Microscopic wireless - Exploring the boundaries of ultra low-power design
机译:
微观无线-探索超低功耗设计的边界
作者:
Rabaey J.M.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
low-power electronics;
transceivers;
wireless channels;
ULP wireless transceivers;
microscopic wireless;
ultra low-power design;
88.
A frequency synthesizer for Mode-1 MB-OFDM UWB applications
机译:
一种用于模式1 MB-OFDM UWB应用的频率合成器
作者:
Jung-Yu Chang
;
Che-Wei Fan
;
Shen-Iuan Liu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
OFDM modulation;
delay lock loops;
field effect MMIC;
frequency synthesizers;
ultra wideband communication;
CMOS process;
Mode-1 MB-OFDM;
UWB applications;
delay-locked loop;
frequency 3.342 GHz to 4.488 GHz;
frequency synthesizer;
multiply-by-two circuit;
noise sensitivity reduction;
power 19.2 mW;
quadrature signals;
size 65 nm;
switching time measurement;
time 1.1 ns;
voltage 1.2 V;
89.
New design method of low power over current protection circuit for low dropout regulator
机译:
低压差稳压器的低功耗过电流保护电路的新设计方法
作者:
Heng S.
;
Weichun Tung
;
Cong-Kha Pham
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
low-power electronics;
overcurrent protection;
CMOS process;
Schmitt trigger;
comparator;
current 200 mA;
low current consumption;
low dropout regulator;
low power overcurrent protection circuit;
regulator output voltage;
size 0.35 mum;
voltage 0.5 V to 5.6 V;
voltage 1.2 V to 3.6 V;
90.
Communication in macrochips using silicon photonics for high-performance and low-energy computing
机译:
使用硅光子进行高性能和低能耗计算的宏芯片中的通信
作者:
Cunningham J.E.
;
Krishnamoorthy A.V.
;
Xuezhe Zheng
;
Guoliang Li
;
Ron Ho
;
Lexau J.
;
Shubin I.
;
Raj K.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS integrated circuits;
electronic engineering computing;
etching;
integrated optoelectronics;
micromachining;
micromirrors;
nanophotonics;
optical communication;
optical interconnections;
silicon;
wavelength division multiplexing;
(100) silicon surface;
CMOS-compatible silicon photonics;
RMS jitter;
amplitude metrics;
bit rate 10 Gbit/s;
chip-to-chip I-O communication;
chip-to-chip optical interconnects;
detectors;
dry etching rib waveguides;
face-to-face optical proximity communication;
high-performance computin;
91.
The future of electrical I/O for microprocessors
机译:
微处理器电子I / O的未来
作者:
OMahony F.
;
Balamurugan G.
;
Jaussi J.E.
;
Kennedy J.
;
Mansuri M.
;
Shekhar S.
;
Casper B.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
CMOS digital integrated circuits;
clocks;
equalisers;
integrated circuit design;
microprocessor chips;
The chip-to-chip communication;
balanced link designs;
clocking;
clocking techniques;
electrical I/O;
electrical signaling;
equalization;
high-level architecture;
high-speed CMOS microprocessor;
link power efficiency;
multi-core processors;
statistical link-level design tools;
I/O;
data link;
electrical;
low-power;
microprocessor;
scaling;
signaling;
transceiver;
wireline;
92.
On calculation of delay range in fault simulation for test cubes
机译:
关于测试立方体故障仿真中延迟范围的计算
作者:
Kajihara S.
;
Oku S.
;
Miyase K.
;
Xiaoqing Wen
;
Sato Y.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
automatic test pattern generation;
delays;
fault simulation;
logic testing;
delay range;
test cubes;
93.
Implementation and verification practices of DVFS and power gating
机译:
DVFS和电源门的实施和验证实践
作者:
Shi-Hao Chen
;
Jiing-Yuan Lin
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
logic circuits;
power aware computing;
power consumption;
dynamic frequency scaling techniques;
dynamic voltage scaling;
interface logics;
leakage power consumption;
leakage power reduction;
multisupply voltage;
power gating;
power shut-off;
power supply voltage reduction;
seamless interface control circuit;
94.
The evolution of interconnect management in physical synthesis
机译:
物理综合中互连管理的发展
作者:
Saxena P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
circuit optimisation;
integrated circuit design;
integrated circuit interconnections;
circuit optimization;
guaranteed net delay;
interconnect management;
physical synthesis;
95.
A reconfigurable architecture for entropy decoding and IDCT in H.264
机译:
H.264中用于熵解码和IDCT的可重构体系结构
作者:
Chia-Cheng Lo
;
Shang-Ta Tsai
;
Ming-Der Shieh
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
adaptive codes;
arithmetic codes;
binary codes;
decoding;
discrete cosine transforms;
entropy codes;
reconfigurable architectures;
video coding;
H.264 standard;
coarse-grain reconfigurable architecture;
context-based adaptive binary arithmetic coding;
context-based adaptive variable length coding;
entropy decoding;
frequency 66 MHz;
inverse discrete cosine transform;
system design;
96.
A built-in self-repair method for RAMs in mesh-based NoCs
机译:
基于网状NoC的RAM的内置自修复方法
作者:
Hsiang-Ning Liu
;
Yu-Jen Huang
;
Jin-Fu Li
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
built-in self test;
integrated circuit interconnections;
integrated circuit reliability;
integrated memory circuits;
logic testing;
network routing;
network-on-chip;
random-access storage;
RAM;
built-in self-repair method;
giga-scale integrated chip;
global spare memory;
mesh-based NoC;
97.
Co-calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADC
机译:
1位/级流水线ADC的电容器失配和比较器失调的共校准
作者:
Xuan-Lun Huang
;
Ping-Ying Kang
;
Yuan-Chi Yu
;
Jiun-Lang Huang
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
analogue-digital conversion;
calibration;
capacitors;
comparators (circuits);
analog-to-digital converters;
capacitor mismatch cocalibration;
capacitor resizing;
comparator offset;
pipelined ADC;
two phase calibration technique;
98.
Scalable and low cost design approach for variable block size motion estimation (VBSME)
机译:
用于可变块大小运动估计(VBSME)的可扩展且低成本的设计方法
作者:
Parandeh-Afshar H.
;
Brisk P.
;
Ienne P.
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
block codes;
motion estimation;
video coding;
VBSME hardware design;
variable block size motion estimation;
99.
High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems
机译:
用于MIMO-OFDM系统的高收敛速度,低计算复杂度的SVD算法
作者:
Cheng-Zhou Zhan
;
Kai-Yuan Jheng
;
Yen-Lian Chen
;
Ting-Jhun Jheng
;
An-Yeu Wu
会议名称:
《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》
|
2009年
关键词:
MIMO communication;
OFDM modulation;
communication complexity;
receiving antennas;
singular value decomposition;
software radio;
transmitting antennas;
wireless channels;
MIMO-OFDM systems;
SVD algorithm;
hardware implementation;
high-convergence-speed low-computation-complexity;
high-spectral efficiency high-channel capacity;
multiple-input multiple-output systems;
orthogonal frequency-division multiplexing;
receiver antenna;
reconfigurable ability;
singular-vector matrix;
spatial multiplexing technique;
transmit;
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