Layout-level design for testability rules for a CMOS cell library

摘要

In CMOS technology there are some faults (opens and shorts) thatnare hard to detect or even undetectable. For this reason layout levelndesign for testability (LLDFT) rules have been developed. These rulesnprevent the faults or reduce the appearance probability of them. Thenpurpose of this work is to apply a practical set of LLDFT rules on thencells of the library designed at the Centre Nacional de Microelectronican(CNM) in order to obtain a highly testable cell library. The authorsnsummarize the main results (area overhead and performance degradation)nof the application of the LLDFT rules on the cells