High Density Copper Bump Technology Integrated With Wafer Level Package

摘要

Sub-100μm fine pitched copper pillars are fabricated using standard semiconductor wafer batch processing techniques. As traditional solder bumps reach their resolution limits, this technology offers performance improvements and compliments advances in flip chip and wafer level packaging technology. A 2-wafer level bonded Ku-Band phase shifter MMIC wafer stack is integrated to PCB assembly with copper pillar interconnects between chip and board, and a fully functional 3-bit phase shifter module has been demonstrated.