Modeling the lithography of ion implantation resists on topography

摘要

With emerging technologies, such as fin-based field-effect transistors (finFETs), the structures, which define the functionality of a device, have added one dimension in the patterning and are now three-dimensional. Lithography for CMOS patterning becomes more complicated for finFETs given the three-dimensional substrate structure, and the resist modeling targeting this issue is yet to be fully investigated. Here, we present lithographic simulations on topography relevant for finFET devices compatible with nodes down to 10 nm. We investigate the influence of different materials and of the additional optical complexity due to the topography and density of the gates and fins.