On-die DFT based solutions are sufficient for testing multi-GHz interfaces in manufacturing (and are also key to enabling lower cost ATE platforms)

摘要

Historically, functional testing of interfaces was used not only to screen defects but also to "truncate" the tail of the silicon fabrication process distribution induced out of spec devices. With the advent of Source Synchronous and High Speed Serial like interfaces, there is no longer a "tail" of performance and therefore it is no longer possible to "bin" based on interface performance without drastically impacting the yield. In addition, the timing specifications are in some instances specified at the PAD and not at the PIN so the external measurement may be very difficult to interpret or be completely misleading. The result is that interface testing, particularly timing oriented testing, will be focused on screening defects at locations that may not be directly visible by ATE.